Method and apparatus for encoding and decoding data

ABSTRACT

A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix H b  and wherein H b  comprises a section H b1  and a section H b2 , and wherein H b2  comprises a first part comprising a column h b  having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere. The expansion of the base matrix H b  uses identical submatrices for 1s in each column of the second part H′ b2 , and the expansion uses paired submatrices for an even number of 1s in h b .

FIELD OF THE INVENTION

The present invention relates generally to encoding and decoding data and in particular, to a method and apparatus for encoding and decoding data utilizing low-density parity-check (LDPC) codes.

BACKGROUND OF THE INVENTION

As described in U.S. patent application Ser. No. 10/839,995, which is incorporated by reference herein, a low-density parity-check (LDPC) code is a linear block code specified by a parity-check matrix H. In general, an LDPC code is defined over a Galois Field GF(q), q≧2. If q=2, the code is a binary code. All linear block codes can be described as the product of a k-bit information vector s_(1×k) with a code generator matrix G_(k×n) to produce an n-bit codeword x_(1×n), where the code rate is r=k/n. The codeword x is transmitted through a noisy channel, and the received signal vector y is passed to the decoder to estimate the information vector s_(1×k).

Given an n-dimensional space, the rows of G span the k-dimensional codeword subspace C, and the rows of the parity-check matrix H_(m×n) span the m-dimensional dual space C^(⊥), where m=n−k. Since x=sG and GH^(T)=0, it follows that xH^(T)=0 for all codewords in subspace C, where “T” (or “T”) denotes matrix transpose. In the discussion of LDPC codes, this is generally written as HX ^(T)=0^(T),  (1) where 0 is a row vector of all zeros, and the codeword x=[s p]=[s₀, s₁, . . . ,s_(k−1), p₀, p₁, . . . , p_(m−1)], where p₀, . . . , p_(m−1) are the parity-check bits; and s₀, . . . , s_(k−1) are the systematic bits, equal to the information bits within the information vector.

For an LDPC code the density of non-zero entries in H is low, i.e., there are only a small percentage of 1's in H, allowing better error-correcting performance and simpler decoding than using a dense H. A parity-check matrix can be also described by a bipartite graph. The bipartite graph is not only a graphic description of the code but also a model for the decoder. In the bipartite graph, a codeword bit (therefore each column of H) is represented by a variable node on the left, and each parity-check equation (therefore each row of H) is represented by a check node on the right. Each variable node corresponds to a column of H and each check node corresponds to a row of H, with “variable node” and “column” of H referred to interchangeably, as are “check node” and “row” of H. The variable nodes are only connected to check nodes, and the check nodes are only connected to variable nodes. For a code with n codeword bits and m parity bits, variable node v_(i) is connected to check node c_(j) by an edge if codeword bit i participates in check equation j, i=0, 1, . . . , n−1, j =0, 1, . . . , m−1. In other words, variable node i is connected to check node j if entry h_(ji) of the parity-check matrix H is 1. Mirroring Equation (1), the variable nodes represent a valid codeword if all check nodes have even parity.

An example is shown below to illustrate the relationship between the parity-check matrix, the parity-check equations, and the bipartite graph. Let an n=12, rate-1/2 code be defined by

$\begin{matrix} {{H = {\underset{\underset{n}{︸}}{\left. \begin{bmatrix} 1 & 0 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 1 & 1 & 0 & 0 \\ 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 \\ 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 \\ 0 & 0 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 1 \end{bmatrix} \right\}}m}},} & (2) \end{matrix}$ with the left side portion corresponding to k (=6) information bits s, the right side portion corresponding to m (=6) parity bits p. Applying (1), the H in (2) defines 6 parity-check equations as follows:

$\begin{matrix} \left\{ {\begin{matrix} {{x_{0} + x_{2} + x_{6} + x_{7}} = 0} \\ {{x_{1} + x_{4} + x_{7} + x_{8}} = 0} \\ {{x_{2} + x_{5} + x_{6} + x_{8} + x_{9}} = 0} \\ {{x_{0} + x_{3} + x_{9} + x_{10}} = 0} \\ {{x_{1} + x_{4} + x_{10} + x_{11}} = 0} \\ {{x_{3} + x_{5} + x_{6} + x_{11}} = 0} \end{matrix}.} \right. & (3) \end{matrix}$ H also has the corresponding bipartite graph shown in FIG. 1.

As discussed above, the receiver obtains a contaminated version y of the transmitted codeword x. To decode y and determine the original information sequence s, an iterative decoding algorithm, such as belief propagation, is applied based on the bipartite graph. Soft information in the format of log-likelihood ratio (LLRs) of the codeword bits is passed between the bank of variable nodes and the bank of check nodes. The iteration is stopped either when all check equations are satisfied or a maximum allowed iteration limit is reached.

A structured LDPC code design starts with a small m_(b)×n_(b) base matrix H_(b), makes z copies of H_(b), and interconnects the z copies to form a large m×n H matrix, where m=m_(b)×z, n=n_(b)×z. Using the matrix representation, to build an H from H_(b) each 1 in H_(b) is replaced by a z×z permutation submatrix, and each 0 in H_(b) is replaced by a z×z all-zero submatrix. This procedure essentially maps each edge of H_(b) to a vector edge of length z in H, each variable node of H_(b) to a vector variable node of length z in H, and each check node of H_(b) to a vector check node of length z in H. The benefits of vectorizing a small matrix H_(b) to build a large matrix H are:

-   -   1. By using a different values of z, codes of rate k_(b)/n_(b),         where k_(b)=n_(b)−m_(b), can be designed for many different         information sequence sizes k=z×k_(b) from a single base matrix         H_(b).     -   2. Memory requirements are greatly reduced. With a structured         LDPC design, only the base matrix H_(b) and the permutation for         its 1's need to be stored, which requires significantly less         memory since H_(b) is typically much smaller than H and the         permutation can be very simple.     -   3. Encoding and decoding can be performed on groups of bits         rather than by single bits. For example, a group of z messages         can be fetched from memory, permuted, and passed between a         vector variable node and a vector check node.

Although the structured LDPC design philosophy greatly reduces the implementation complexity, a technique does not exist for designing the base matrix and assigning the permutation matrices for a given target H size which results in a LDPC code that has good error-correcting performance and can be efficiently encoded and decoded. Therefore, a need exists for a method and apparatus for designing a structured H and a method and apparatus for encoding and decoding data utilizing the structured H matrix.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates the bipartite graph of an (12, 6) H matrix.

FIG. 2 illustrates the relationships between the base matrix H_(b), the model matrix H_(bm), and the final expanded matrix H.

FIG. 3 is a block diagram of an encoder.

FIG. 4 is a block diagram of a decoder.

FIG. 5 is a flow chart showing the operation of the encoder of FIG. 3.

FIG. 6 is a flow chart showing the operation of the decoder of FIG. 4.

DETAILED DESCRIPTION OF THE DRAWINGS

To address the above-mentioned need, a structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix H_(b) and wherein H_(b) comprises a section H_(b1) and a section H_(b2), and wherein H_(b2) comprises a first part comprising a column h_(b) having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere. The expansion of the base matrix H_(b) uses identical submatrices for 1s in each column of the second part H′_(b2), and the expansion uses paired submatrices for an even number of 1s in h_(b).

The present invention encompasses a method for operating a transmitter that generates parity-check bits p=(p₀, . . . , p_(m−1)) based on a current symbol set s=(s₀, . . . , s_(k−1)). The method comprises the steps of receiving the current symbol set s=(s₀, . . . , s_(k−1)), and using a matrix H to determine the parity-check bits. The parity-check bits are transmitted along with the current symbol set. Matrix H is an expansion of a base matrix H_(b) where H_(b) comprises a section H_(b1) and a section H_(b2), and wherein H_(b2) comprises a first part comprising a column h_(b) having an odd weight greater than 2, and a second part H′_(b2) comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere. The expansion of the base matrix H_(b) uses identical submatrices for 1s in each column of the second part H′_(b2), and wherein the expansion uses paired submatrices for an even number of 1s in h_(b).

The present invention additionally encompasses a method for operating a receiver that estimates a current symbol set s=(s₀, . . . , s_(k−1)). The method comprises the steps of receiving a received signal vector y=(y₀ . . . y_(n−1)) and using a matrix H to estimate the current symbol set s=(s₀, . . . , s_(k−1)). Matrix H is an expansion of a base matrix H_(b) and wherein H_(b) comprises a section H_(b1) and a section H_(b2), with H_(b2) comprising a first part comprising a column h_(b) having an odd weight greater than 2, and a second part H′_(b2) comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere. The expansion of the base matrix H_(b) uses identical submatrices for is in each column of the second part H′_(b2), and wherein the expansion uses paired submatrices for an even number of 1s in h_(b).

The present invention additionally encompasses an apparatus comprising storage means for storing a matrix H, a microprocessor using a matrix H to determine parity-check bits, wherein H is an expansion of a base matrix H_(b) and H_(b) comprises a section H_(b1) and a section H_(b2), with H_(b2) comprising a first part comprising a column h_(b) having an odd weight greater than 2, and a second part H′_(b2) comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere. The expansion of the base matrix H_(b) uses identical submatrices for 1s in each column of the second part H′_(b2), and wherein the expansion uses paired submatrices for an even number of 1s in h_(b).

The present invention encompasses an apparatus comprising storage means for storing a matrix H, a receiver for receiving a signal vector y=(y₀ . . . y_(n−1)), and a microprocessor using a matrix H to determine a current symbol set (s₀, . . . , s_(k−1)). Matrix H is an expansion of a base matrix H_(b) with H_(b) comprising a section H_(b1) and a section H_(b2), and wherein H_(b2) comprises a first part comprising a column h_(b) having an odd weight greater than 2. H_(b2) comprises a second part H′_(b2) having matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere. Two identical submatrices are used to expand 1s in every column of H′_(b2), and paired submatrices are used to expand an even number of 1s in h_(b).

Turning now to the drawings, wherein like numerals designate like components, FIG. 3 is a block diagram of encoder 300 in accordance with a first embodiment of the present invention. As shown, encoder 300 comprises microprocessor 301 and lookup table 303. In the first embodiment of the present invention, microprocessor 301 comprises a digital signal processor (DSP), such as, but not limited to MSC8300 and DSP56300 DSPs. Additionally, lookup table 303 serves as storage means to store a matrix, and comprises read-only memory; however, one of ordinary skill in the art will recognize that other forms of memory (e.g., random-access memory, magnetic storage memory, etc.) may be utilized as well. In a second embodiment, the functionality of the microprocessor 301 and the lookup table 303 can be incorporated into an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). In particular, the lookup table 303 can be implemented in a form of memory corresponding to the existence or non-existence of signal paths in a circuit.

As discussed above, encoded data is generally output as a plurality of parity-check bits in addition to the systematic bits, where together the parity-check and systematic bits form a codeword x. In the first embodiment of the present invention, a parity-check matrix H is stored in lookup table 303, and is accessed by microprocessor 301 to solve Equation (1). In particular, microprocessor 301 determines appropriate values for the parity-check bits p=(p₀, . . . , p_(m−1)) based on the current symbol set s=(s₀, . . . , s_(k−1)) and the parity-check matrix H. The parity-check bits and the symbol set are then passed to a transmitter and transmitted to a receiver.

FIG. 4 is a block diagram of decoder 400 in accordance with one embodiment of the present invention. As shown, decoder 400 comprises microprocessor 401 and lookup table 403. In a first embodiment of the present invention, microprocessor 401 comprises a digital signal processor (DSP), such as, but not limited to MSC8300 and DSP56300 DSPs. Additionally, lookup table 403 acts as storage means for storing matrix H, and comprises read-only memory. However, one of ordinary skill in the art will recognize that other forms of memory (e.g., random-access memory, magnetic storage memory, etc.) may be utilized as well. In a second embodiment, the functionality of the microprocessor 401 and the lookup table 403 can be incorporated into an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). In particular, the lookup table 403 can be implemented in a form of memory corresponding to the existence or non-existence of signal paths in a circuit.

The received signal vector (received via a receiver) y=(y₀, . . . , y_(n−1)) corresponds to the codeword x transmitted through a noisy channel, where the encoded data x, as discussed above, is a codeword vector. In the first embodiment of the present invention, a parity-check matrix H is stored in lookup table 403, and is accessed by microprocessor 401 to decode y and estimate the current symbol set s (i.e., the current symbol set (s₀, . . . , s_(k−1))). In particular, microprocessor 401 estimates the current symbol set (s₀, . . . , s_(k−1)) based on the received signal vector y=(y₀, . . . , y_(n−1)) and the parity-check matrix H.

As is well known in the art, there are many ways the decoder 400 can use the parity-check matrix H in the microprocessor 401 for decoding. One such way is to perform a vector-matrix multiplication with H to determine a likely error pattern. Another such way is to use H to construct a bipartite graph where the edges in the graph correspond to 1's in H, and to iteratively process y on the bipartite graph.

For a structured LDPC, the z×z submatrix may be a permutation matrix, a sum of permutation matrices, or any type of binary matrix. Since a permutation matrix P has a single 1 in each row and a single 1 in each column, the weight distribution of the expanded matrix H is the same as the base matrix H_(b) if the permutation submatrix is used. Therefore, the weight distribution of H_(b) is chosen as close to the desired final weight distribution as possible. The following description is illustrative of the case where the entries of H_(b) are replaced by permutation matrices, though any matrices may be used. If a permutation submatrix P_(z×z) of a vector edge has a 1 at (row, column) entry (p(i), i), then the i-th edge within the vector edge is permuted to the p(i)-th position before the vector edge is connected to the vector check node. In other words, this permutation makes the i-th variable node within the related vector variable node connected to the p(i)-th check node within the related vector check node.

The permutations comprising H can be very simple without compromising performance, such as simple cyclic shifts and/or bit-reversals. For instance, a simple circular right shift can be used. With this constraint, each H matrix can be uniquely represented by a m_(b)×n_(b) model matrix H_(bm), which can be obtained by

-   -   replacing each 0 in H_(b) by −1 to denote a z×z all-zero         submatrix, and     -   replacing each h_(i,j)=1 in H_(b) by a circular shift size         p(i,j) where p(i,j) is non-negative.

Since circular left shift (x mod z) times is equivalent to circular right shift ((z−x) mod z) times, it is adequate to discuss circular right shift and refer it as a circular shift for brevity. As discussed previously, there is a one-to-one mapping between H and H_(bm). Therefore, H_(bm) is a shorthand representation of H if z is given. Notationally, the model matrix is distinguished from the base matrix by the subscript ‘bm’, and the expanded matrix is distinguished by removing the subscript ‘bm’. The relationship between the three matrices is illustrated in FIG. 2. Using the structure, the code has error-correcting performance similar to a random H of size m×n, while encoding and decoding are performed based on a much smaller H_(bm).

For example, the matrix of Equation (2) may be used as a base matrix H_(b) to build a model matrix H_(bm) as follows:

$\begin{matrix} {H_{bm} = {\underset{\underset{n_{b}}{︸}}{\left. \begin{bmatrix} 1 & {- 1} & 0 & {- 1} & {- 1} & {- 1} & 0 & 0 & {- 1} & {- 1} & {- 1} & {- 1} \\ {- 1} & 2 & {- 1} & {- 1} & 0 & {- 1} & {- 1} & 0 & 0 & {- 1} & {- 1} & {- 1} \\ {- 1} & {- 1} & 1 & {- 1} & {- 1} & 2 & 2 & {- 1} & 0 & 0 & {- 1} & {- 1} \\ 2 & {- 1} & {- 1} & 1 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 0 & 0 & {- 1} \\ {- 1} & 1 & {- 1} & {- 1} & 0 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 0 & 0 \\ {- 1} & {- 1} & {- 1} & 0 & {- 1} & 1 & 0 & {- 1} & {- 1} & {- 1} & {- 1} & 0 \end{bmatrix} \right\}}{m_{b}.}}} & (4) \end{matrix}$ When z=3, H_(bm) is converted to a (m_(b)×z)×(n_(b)×z) matrix H by replacing each −1 with a 3×3 all-zero submatrix and each i with submatrix P_(i), i=0, 1, 2, where

${P_{0} = \begin{bmatrix} 1 & 0 & 0 \\ 0 & 1 & 0 \\ 0 & 0 & 1 \end{bmatrix}},{P_{1} = \begin{bmatrix} 0 & 1 & 0 \\ 0 & 0 & 1 \\ 1 & 0 & 0 \end{bmatrix}},{P_{2} = {\begin{bmatrix} 0 & 0 & 1 \\ 1 & 0 & 0 \\ 0 & 1 & 0 \end{bmatrix}.}}$ Note that P₀ is the identity matrix, and the columns of P_(i), i>0, are the columns of P₀ circular right shifted i times.

Given a vector q=[q₀, q₁, q₂], qP₀=[q₀, q₁, q₂], qP₁=[q₂, q₀, q₁], qP₂=[q₁, q₂, q₀]. In other words, q P_(i) results in circular right shift of the vector q. On the other hand, P_(i)q^(T), results in circular upper shift of q^(T), or equivalently circular left shift of q. Similar rules apply when a z×z matrix Q is used: QP_(i) results in circular right shift of the columns of Q, P_(i)Q results in circular upper shift of the rows of Q.

Base Matrix H

For an LDPC code without vectorization, an H matrix with a modified staircase structure for the parity part of H leads to efficient encoding without compromising performance. In general, assuming x=[s p]=[s₀, s₁, . . . , s_(k−1), p₀, p₁, . . . ,p_(m−1)], an m-by-n H matrix can be divided into two submatrices, H=[H₁H₂],  (5) where H₂ has a modified staircase structure, and H₁ can be any binary matrix of size m-by-k. This same structure can be used to build the base matrix H_(b) in a structured LDPC design. Similarly, using the modified staircase structure, H_(b) can be partitioned into two sections, where H_(b1) corresponds to the systematic bits s, H_(b2) corresponds to the parity-check bits p: H _(b)=[(H _(b1))_(m) _(b) _(×k) _(b)

(H _(b2))_(m) _(b) _(×m) _(b) ].  (6) Section H_(b2) can be further partitioned into two sections, where vector h_(b) has odd weight w_(h), and H′_(b2) has a staircase structure:

$\begin{matrix} \begin{matrix} {H_{b2} = \begin{bmatrix} h_{b} & H_{b2}^{\prime} \end{bmatrix}} \\ {= {\begin{bmatrix} {h_{b}(0)} & 1 & \; & \; & \; & \; \\ {h_{b}(1)} & 1 & 1 & \; & 0 & \; \\ . & \; & 1 & ⋰ & \; & \; \\ . & \; & \; & ⋰ & 1 & \; \\ . & \; & 0 & \; & 1 & 1 \\ {h_{b}\left( {m_{b} - 1} \right)} & \; & \; & \; & \; & 1 \end{bmatrix}.}} \end{matrix} & (7) \end{matrix}$ Section H_(b1) can be built randomly. Preferably the entire matrix H_(b) has a weight distribution as close to the desired weight distribution as possible. Shift Sizes

To convert the base matrix H_(b) to the m_(b)×n_(b) model matrix H_(bm) (which expands to H), the circular shift sizes p(i,j) need to be determined for each 1 in H_(b). The shift sizes can be first specified for the H₂. After the shift sizes for the H₂ section are determined, the H₁ section shift sizes can be determined to achieve overall good performance of H. The H₁ portion of the base matrix and the shift sizes of the H₁ portion of the base matrix (section H_(bm1)) can be assigned in many different ways. For example, random values for the shift sizes may be selected and accepted if the shift sizes do not cause significant performance degradation. Performance degradation may result from the introduction of excessive numbers of short-length cycles or low-weight codewords. Other techniques available in the LDPC art may also be used.

The circular shift sizes p(i,j) for a given target H size should be specified to allow efficient encoding without compromising decoding performance. To facilitate encoding, the shifts may be assigned such that all but one of the shift matrices corresponding to 1's in h_(b) cancel when added together, and all vector rows of H′_(b2) cancel when summed up. This translates to assigning shift sizes to h_(b) in pairs except for one entry, and assigning the same shift size to both 1's in each column of H′_(b2). For example, if h_(b)=[1 0 0 1 0 0 1]^(T), it is acceptable to have h_(bm)=[3−1−1 3−1−1 4]^(T) as the corresponding column in the model matrix since shift size 3 is assigned in pairs. Since all of the non-zero entries (both 1's) in each column H′_(b2) are assigned the same shift sizes, any shift size option is equivalent to the shift size of 0 (i.e., identity submatrices) plus a permutation of the bits within the vector column. Thus, all shift sizes of H′_(b2) can be assigned 0 for convenience, i.e., each 1 in H′_(b2) is replaced by a z×z identity submatrix when expanding to H.

Due to existence of cycles, the shift sizes of h_(bm) should be assigned carefully. Rules can be applied to avoid forming short cycles or low weight codewords. One property that can be used to avoid cycles is:

If 2c edges form a cycle of length 2c in base matrix H_(b), then the corresponding 2c vector edges form z cycles of length 2c in the expanded matrix H if and only if

$\begin{matrix} {{{\sum\limits_{\underset{{j = 0},\mspace{11mu}\ldots\;,{c - 1}}{i = {2j}}}{p(i)}} = {\sum\limits_{\underset{{j = 0},\mspace{11mu}\ldots\mspace{11mu},{c - 1}}{i = {{2j} + 1}}}{{p(i)}\mspace{14mu}{mod}\mspace{14mu} z}}},} & (8) \end{matrix}$ where z is the expansion factor, p(i) is the circular shift size of edge i in the model matrix H_(bm), and edge 0, 1, 2, . . . , 2c−1 (in this order) form a cycle in H_(b).

Due to the structure of H_(b2), cycles exist between h_(b) and H′_(b2). Thus any two identical shift sizes in h_(bm) would result in replicating the cycle z times in the expanded matrix H according to the above property. However, if these two shifts are located far apart, then the cycles have long length, and have little effect on iterative decoding. Therefore, in a preferred embodiment, when h_(b) of the base matrix has three 1s, to maximize the cycle length, two 1s that are assigned equal shift sizes can be located at the top and the bottom of h_(bm) (as far apart as possible), while leaving one 1 in the middle of h_(b) with an unpaired shift size. For instance, h_(bm)=[3−1 3−1−1−1 4]^(T) would result in z cycles of length 6 between h and H′₂, while h_(bm)=[3−1 4−1−1−1 3]^(T) would result in z cycles of length 14 between h and H′₂, where h and H′₂ are expanded from h_(b) and H′_(b2).

In summary, the H_(b2) section is mapped to the model matrix

$\begin{matrix} \begin{matrix} {H_{bm2} = \begin{bmatrix} h_{bm} & H_{bm2}^{\prime} \end{bmatrix}} \\ {{= \begin{bmatrix} {p\left( {0,k_{b}} \right)} & {p\left( {0,{k_{b} + 1}} \right)} & \; & \; & \; & \; \\ {p\left( {1,k_{b}} \right)} & {p\left( {1,{k_{b} + 1}} \right)} & {p\left( {1,{k_{b} + 2}} \right)} & \; & \; & \; \\ \vdots & \; & {p\left( {2,{k_{b} + 2}} \right)} & ⋰ & \; & \; \\ \; & \; & \; & ⋰ & {p\left( {{m_{b} - 3},{n_{b} - 2}} \right)} & \; \\ \; & \; & \; & \; & {p\left( {{m_{b} - 2},{n_{b} - 2}} \right)} & {p\left( {{m_{b} - 2},{n_{b} - 1}} \right)} \\ {p\left( {{m_{b} - 1},k_{b}} \right)} & \; & \; & \; & \; & {p\left( {{m_{b} - 1},{n_{b} - 1}} \right)} \end{bmatrix}},} \end{matrix} & (9) \end{matrix}$ where k_(b)=n_(b)−m_(b), there are w_(h) (odd, w_(h)>=3) nonnegative entries in h_(bm), and the −1 entries in H′_(bm2) are left blank for brevity. All p(i,k_(b)) values appear an even number of times in h_(bm) except for one, which may be mapped to any non-zero submatrix. Therefore, all w_(h) shifts could be given the same value (e.g., 0), since w_(h) is odd. For H′_(bm2), p(i,j)=p(i+1,j), j=k_(b)+1,k_(b)+2, . . . , n_(b)−1, i=j−k_(b)−1. In the preferred embodiment, assuming w_(h)=3, one example has h_(bm)=[0−1 . . . −1 p_(h)−1 . . . −1 . . . 0]^(T), p_(h) mod z ≠0, and p(i,j)=p(i+1,j)=0, j=k_(b)+1,k_(b)+2, . . . , n_(b)−1, i=j−k_(b)−1 in the H′_(bm2) portion.

Although the discussion above focused on using submatrices that are circular shifts of the identity matrix, in general, any other submatrices may be used (and be represented in an equivalent to the base model matrix). In order to facilitate encoding, the constraints are then:

-   -   1. In every column of H′_(bm2), the two non-zero submatrices are         identical;     -   2. The w_(h) (odd, w_(h)>=3) non-zero submatrices of h_(bm) are         paired (i.e., one submatrix is identical to another submatrix),         except for one submatrix, which can be any non-zero matrix.         Encoding

Encoding is the process of determining the parity sequence p given an information sequence s. To encode the structured LDPC code, each operation is performed over a group of z bits instead of a single bit. Alternatively, vector operations do not have to be used, and the equations below are implemented in equivalent scalar form. To encode, s is divided into k_(b)=n_(b)−m_(b) groups of z bits. Let this grouped s be denoted u, u=[u(0) u(1) . . . u(k _(b−1))],  (10) where each element of u is a column vector as follows u(i)=[s _(iz) s _(iz+1) . . . s _((i+1)z−1)]^(T).  (11)

Using the model matrix H_(bm), the parity sequence p is determined in groups of z. Let the grouped p be denoted v, v=[v(0) v(1) . . . v(m _(b)−1)],  (12) where each element of v is a column vector as follows v(i)=[p _(iz) p _(iz+1) . . . p _((i+1)z−1)]^(T).  (13) Encoding proceeds in two steps, (a) initialization, which determines v(0), and (b) recursion, which determines v(i+1) from v(i), 0≦i≦m_(b)−2.

An expression for v(0) can be derived by summing over the rows of Equation (1) to obtain

$\begin{matrix} {{P_{p{({x,k_{b}})}}{v(0)}} = {\sum\limits_{j = 0}^{k_{b} - 1}{\sum\limits_{i = 0}^{m_{b} - 1}{P_{p{({i,j})}}{u(j)}}}}} & (14) \end{matrix}$ where x is the row index of h_(bm) where the entry is nonnegative and is used an odd number of times. In the preferred embodiment, the top and bottom entries of h_(bm) are paired, thus 1≦x≦m_(b)−2. Equation (14) is solved for v(0) by multiplying both sides by P_(p(x,k) _(b) )⁻¹. For the special case considered here where p(x,k_(b)) represents a circular shift, P_(p(x,k) _(b) ₎ ⁻¹=P_(z−p(x,k) _(b) ₎. In other words, v(0) is obtained by

$\begin{matrix} {{v(0)} = {P_{z - {p{({x,k_{b}})}}}{\sum\limits_{j = 0}^{k_{b} - 1}{\sum\limits_{i = 0}^{m_{b} - 1}{P_{p{({i,j})}}{{u(j)}.}}}}}} & (15) \end{matrix}$

In general, the recursions expressed in Equations (16) and (17) can be derived by considering the structure of H′_(b2),

$\begin{matrix} {{{P_{p{({i,{k_{b} + 1}})}}{v(1)}} = {{\sum\limits_{j = 0}^{k_{b} - 1}{P_{p{({i,j})}}{u(j)}}} + {P_{p{({i,k_{b}})}}{v(0)}}}},{i = 0},} & (16) \end{matrix}$ and

$\begin{matrix} \begin{matrix} {{{P_{p{({i,{k_{b} + i + 1}})}}{v\left( {i + 1} \right)}} = {{P_{p{({i,{k_{b} + i}})}}{v(i)}} + {\sum\limits_{j = 0}^{k_{b} - 1}{P_{p{({i,j})}}{u(j)}}} + {P_{p{({i,k_{b}})}}{v(0)}}}},} \\ {{i = 1},\ldots\mspace{11mu},{m_{b} - 2},} \end{matrix} & (17) \end{matrix}$ where P ⁻¹≡0_(z×z.)  (18)

Thus all parity bits not in v(0) are determined by iteratively evaluating Equations (16) and (17) for 0≦i≦m_(b)−2.

In a preferred embodiment where the shifts sizes of the 1's in H′_(b2) are all zero, Equations (16) and (17) can be simplified to Equations (19) and (20),

$\begin{matrix} \begin{matrix} {{{v(1)} = {{\sum\limits_{j = 0}^{k_{b} - 1}{P_{p{({i,j})}}{u(j)}}} + {P_{p{({i,k_{b}})}}\;{v(0)}}}},} & {{i = 0},} \end{matrix} & (19) \end{matrix}$ and

$\begin{matrix} \begin{matrix} {{{v\left( {i + 1} \right)} = {{v(i)} + {\sum\limits_{j = 0}^{k_{b} - 1}{P_{p{({i,j})}}{u(j)}}} + {P_{p{({i,k_{b}})}}{v(0)}}}},} \\ {{i = 1},\ldots\mspace{11mu},{m_{b} - 2.}} \end{matrix} & (20) \end{matrix}$

Thus, as in the general case, all parity bits not in v(0) are determined by iteratively evaluating Equation (19) and (20) for 0≦i≦m_(b)−2.

Equations (14), (19), and (20) describe the encoding algorithm. These equations also have a straightforward interpretation in terms of standard digital logic architectures. First, since the non-negative elements p(i,j) of H_(bm) represent circular shift sizes of a vector, all products of the form P_(p(i,j))u(j) can be implemented by a size-z barrel shifter. A circular shift size of zero may not need to be barrel-shifted. Since a barrel shifter that implements all possible circular shifts must provide connections from each input bit to all output bits, the speed with which it can be run depends upon z. For a given z, complexity can be reduced and speed increased by allowing only a proper subset of all possible circular shifts. For instance, H_(bm) could be constructed with only even circular shift sizes. The summations in Equations (14), (19), and (20) represent vector-wise XOR (exclusive OR) operations that are gated (i.e., do not update) when p(i,j)=−1.

To implement the summations in Equations (14), (19), and (20) the entries p(i,j) of H_(bm), 0≦i≦k_(b), 0≦j≦m_(b)−1, can be stored in a read-only memory (ROM) of width ┌log₂ z┐+1 bits. The grouped information sequence can be stored in a size-z memory, which can be read out in sequential order. As each information vector u(j) is read out, the corresponding entry from the H_(bm) ROM can be read out, which instructs the barrel shifter of the necessary circular shift. After the circular shift, a register containing a partial summation is updated. For Equation (14), after each inner summation is completed, the result can be used to update another register containing the outer summation. When the outer summation is complete, it can be circularly shifted by z−p(x,k_(b)).

Assuming the barrel shifting can be implemented in a single clock cycle, encoding can be accomplished in approximately (k_(b)+1)m_(b) clock cycles. This number can be reduced at the expense of m_(b)−1 extra z-wide registers by computing and storing the summations of Equation (19) and (20), using results that become available as Equation (14) is being computed.

Extending the Matrix

The code extension procedure can be applied to the structured code to reach a lower-rate code. Progressively lower-rate code can be used in successive transmissions of an incremental redundancy (IR) procedure. Specifically, if the model matrix of the 1^(st) transmission is

$\begin{matrix} {{H_{bm}^{(1)} = \begin{bmatrix} H_{bm1}^{(1)} & H_{bm2}^{(1)} \end{bmatrix}},} & (21) \end{matrix}$ then the model matrix for the 2^(nd) transmission may use

$\begin{matrix} {{H_{bm}^{(2)} = \begin{bmatrix} \begin{matrix} H_{bm1}^{(1)} & H_{bm2}^{(1)} \end{matrix} & 0 \\ H_{bm1}^{(2)} & H_{bm2}^{(2)} \end{bmatrix}},} & (22) \end{matrix}$ etc., where for each transmission i, submatrix H_(bm2) ^((i)) has the format in (9) and has size m_(b) ^((i))×m_(b) ^((i)). The first transmission may send n_(b) ⁽¹⁾=k_(b)+m_(b) ⁽¹⁾ groups of bits, └u(0),u(1), . . . , u(k_(b)−1), v⁽¹⁾(0), v⁽¹⁾(1), . . . , v⁽¹⁾(m_(b) ⁽¹⁾−1)┘, each group having size z. The decoding after the 1^(st) transmission is performed using received signals of └u(0),u(1), . . . , u(k_(b)−1), v⁽¹⁾(0), v⁽¹⁾(1), . . . , v⁽¹⁾(m_(b) ⁽¹⁾−1)┘ and (21). The 2^(nd) transmission may send another m_(b) ⁽²⁾ groups of bits of size z, └v⁽²⁾(0), v⁽²⁾(1), . . . , v⁽²⁾(m_(b) ⁽²⁾−1)┘, where m₂=m_(b) ⁽²⁾z, and the bits of the first transmission and the second transmission together, └u(0), u(1), . . . , u(k_(b)−1), v⁽¹⁾(0), v⁽¹⁾(1), . . . , v⁽¹⁾(m_(b) ⁽¹⁾−1), v⁽²⁾(0), v⁽²⁾(1), . . . , v⁽²⁾(m_(b) ⁽²⁾−1)┘, are a codeword corresponding to (22). Therefore, the decoding after the second transmission is performed based on (22) and the combined received signal from the 1^(st) transmission and the 2^(nd) transmission. This procedure may be repeated for more transmissions. The decoding after the 2^(nd) transmission is based on a code of rate k_(b)/n_(b) ⁽²⁾=k_(b)/(n_(b) ⁽¹⁾+m_(b) ⁽²⁾), which is lower than that of 1^(st) transmission. This procedure may be repeated for more transmissions, with each additional transmission contributing to a stronger, lower-rate code.

FIG. 5 is a flow chart showing the operation of encoder 300, and in particular, microprocessor 301. The logic flow begins at step 501 where a current symbol set (s₀, . . . , s_(k−1)) is received by microprocessor 301. At step 503, values of parity-check bits are determined based on the current symbol set and H. In particular, the parity-check bits (p₀, . . . , p_(m−1)) are determined as described above, with H being an expansion of a base matrix H_(b). As discussed, H_(b) comprises a section H_(b), and a section H_(b2), and wherein H_(b2) comprises a first part comprising a column h_(b) having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere. In addition, the expansion of the base matrix H_(b) (to produce H) uses identical submatrices for the 1s in each column of the second part H′_(b2), and wherein the expansion uses paired submatrices for an even number of 1s in h_(b). At step 505 the current symbol set and the parity-check bits are transmitted via over-the-air transmission.

FIG. 6 is a flow chart showing the operation of decoder 400, and in particular, microprocessor 401. The logic flow begins at step 601 where the received signal vector y=(y₀, . . . , y⁻¹) is received. At step 603, estimates of the current symbol set s (i.e., the current symbol set (s₀, . . . , s_(k−1))) are determined based on H. As discussed, H is an expansion of a base matrix H_(b) and wherein H_(b) comprises a section H_(b1) and a section H_(b2), and wherein H_(b2) comprises a first part comprising a column h_(b) having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere.

While the invention has been particularly shown and described with reference to a particular embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, while the invention has been shown with the ordering of s_(i) and p_(i) within x defined, one of ordinary skill in the art will recognize that other ordering of the bits within x can occur since the codeword bits can be collected in any order as long as the columns of H are reordered accordingly. Additionally, while the above-description has been particularly shown and described with reference to binary codes (i.e., codes defined over the Galois Field GF(2)), one of ordinary skill in the art will recognize that an arbitrary GF may be utilized as well. Although the examples given above are shown in one format, other formats are possible which allow similar encoding and code modification procedure. For example, the rows of H may be permuted without affecting the value of the parity-check bits. In another example, the modified staircase structure may be used for a subset of the parity-check bits. In yet another example, additional steps may be performed when expanding the base matrix to the expanded matrix. The matrix H may also be used in any type of decoder that relies upon a parity-check matrix. It is intended that such changes come within the scope of the following claims. 

1. A method for operating a transmitter that generates parity-check bits p=(p₀, . . . , p_(m−1)) based on a current symbol set s=(s₀, . . . , s_(k−1)), the method comprising the steps of: receiving the current symbol set s=(s₀, . . . , s_(k−1)); using a matrix H to determine the parity-check bits; and transmitting the parity-check bits along with the current symbol set; wherein H is an expansion of a base matrix H_(b) with H_(b) comprising a section H_(b1) and a section H_(b2), with H_(b2) comprising a first part having a column h_(b) having an odd weight greater than 2, and a second part H′_(b2) comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, 0 elsewhere; and wherein the expansion of the base matrix H_(b) uses identical submatrices for 1s in each column of the second part H′_(b2), and wherein the expansion uses paired submatrices for an even number of 1s in h_(b).
 2. The method of claim 1 wherein H_(b) is expanded by replacing each entry of H_(b) with a size z×z submatrix to produce H.
 3. The method of claim 1 wherein H_(b) is expanded by replacing each zero element of H_(b) with a zero submatrix of size z×z to produce H.
 4. The method of claim 1 wherein H_(b) is expanded by replacing each non-zero element of H_(b) with a non-zero submatrix to produce H.
 5. The method of claim 1 wherein H_(b) is expanded by replacing each non-zero element of H_(b) with a non-zero permutation submatrix to produce H.
 6. The method of claim 1 wherein: $\begin{matrix} {H_{b2} = \begin{bmatrix} h_{b} & H_{b2}^{\prime} \end{bmatrix}} \\ {{= \begin{bmatrix} {h_{b}(0)} & 1 & \; & \; & \; & \; \\ {h_{b}(1)} & 1 & 1 & \; & 0 & \; \\ . & \; & 1 & ⋰ & \; & \; \\ . & \; & \; & ⋰ & 1 & \; \\ . & \; & 0 & \; & 1 & 1 \\ {h_{b}\left( {m_{b} - 1} \right)} & \; & \; & \; & \; & 1 \end{bmatrix}},} \end{matrix}$ where vector h_(b) has an odd weight w_(h)>=3.
 7. The method of claim 6 wherein H_(b) is expanded by replacing each 1 within a same column of H′_(b2) with a same z×z non-zero submatrix to produce H.
 8. The method of claim 6 wherein H_(b) is expanded by replacing each 1 within a same column of H′_(b2) with a same z×z non-zero submatrix that has a same circular shift size to produce H.
 9. The method of claim 6 wherein H_(b) is expanded by replacing each 1 within a same column of H′_(b2) with a same identity matrix to produce H.
 10. The method of claim 1 wherein the step of using matrix H to determine the parity-check bits P=(p₀, . . . , P_(m−1)) comprises the step of determining ${{v(0)} = {P_{z - {p{({x,k_{b}})}}}\;{\sum\limits_{j = 0}^{k_{b} - 1}{\sum\limits_{i = 0}^{m_{b} - 1}{P_{p{({i,j})}}{u(j)}}}}}},$ where u=[u(0) u(1) . . . u(k_(b)−1)] is the current symbol set s grouped into k_(b) groups of z bits, v=[v(0) v(1) . . . v(m_(b)−1)] is the parity-check bits p grouped into m_(b) groups of z bits, p(i,j) is a shift size, and multiplication by P_(x) circularly shifts a vector by x positions.
 11. The method of claim 1 wherein the step of using matrix H to determine the parity-check bits (p₀, . . . , P_(m−1)) comprises the step of determining ${v(0)} = {P_{z - {p{({x,k_{b}})}}}\;{\sum\limits_{j = 0}^{k_{b} - 1}{\sum\limits_{i = 0}^{m_{b} - 1}{P_{p{({i,j})}}{u(j)}}}}}$ and determining v(1), v(2), . . . , v(m_(b)−1) recursively via $\begin{matrix} {{{v(1)} = {{\sum\limits_{j = 0}^{k_{b} - 1}{P_{p{({i,j})}}{n(j)}}} + {P_{p{({i,k_{b}})}}{v(0)}}}},} & {{i = 0},} \\ {{{v\left( {i + 1} \right)} = {{v(i)} + {\sum\limits_{j = 0}^{k_{b} - 1}{P_{p{({i,j})}}{u(j)}}} + {P_{p{({i,k_{b}})}}{v(0)}}}},} & {{i = 1},\ldots\mspace{11mu},{m_{b} - 2},} \end{matrix}$ where u=[u(0) u(1) . . . u(k_(b)−1)] is the current symbol set s grouped into k_(b) groups of z bits, v=[v(0) v(1) . . . v(m_(b)−1)] is the parity-check bits p grouped into m_(b) groups of z bits, p(i,j) is a shift size, and multiplication by P_(x) circularly shifts a vector by x positions.
 12. The method of claim 1 wherein the step of using matrix H to determine the parity-check bits (P₀, . . . , p_(m−1)) comprises the step of determining ${v(0)} = {P_{z - {p{({x,k_{b}})}}}{\sum\limits_{j = 0}^{k_{b} - 1}{\sum\limits_{i = 0}^{m_{b} - 1}{P_{p{({i,j})}}\;{u(j)}}}}}$ and determining v(1), v(2), . . . , v(m_(b)−1) recursively, where u=[u(0) u(1) . . . u(k_(b)−1)] is the current symbol set s grouped into k_(b) groups of z bits, v=[v(0) v(1) . . . v(m_(b)−1)] is the parity-check bits p grouped into m_(b) groups of z bits, p(i,j) is a shift size, and multiplication by P_(x) circularly shifts a vector by x positions.
 13. The method of claim 1 further comprising the steps of: determining additional parity-check bits need to be transmitted; and transmitting the additional parity-check bits (p_(m), . . . , P_(m+m) ₂ ⁻¹) based on the current symbol set s=(s₀, . . . , s_(k−1)) and p=(p₀, . . . , p_(m−1)), where m₂=m_(b) ⁽²⁾z.
 14. The method of claim 13 further comprising the step of using a model matrix H⁽²⁾ _(bm) to determine the additional parity-check bits wherein H⁽²⁾ _(bm) is based on H_(bm).
 15. The method of claim 14 wherein H⁽²⁾ _(bm) comprises a section H⁽²⁾ _(bm2), wherein the base matrix of H⁽²⁾ _(bm2) comprises a first column h_(b) ⁽²⁾ having an odd weight greater than 2, and a second part H′_(b2) ⁽²⁾ comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, 0 elsewhere; and wherein two identical submatrices are used to expand 1s in every column of H′_(b2) ⁽²⁾ and paired submatrices are used to expand an even number of 1s in h_(b) ⁽²⁾.
 16. A method for operating a receiver that estimates a current symbol set s=(s₀, . . . , s_(k−1)), the method comprising the steps of: receiving a received signal vector y=(y₀ . . . y_(n−1)); and using a matrix H to estimate the current symbol set s=(s₀, . . . , s_(k−1)), wherein H is an expansion of a base matrix H_(b) with H_(b) comprising a section H_(b1) and a section H_(b2), and wherein H_(b2) comprises a first part comprising a column h_(b) having an odd weight greater than 2, and a second part H′_(b2) comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, 0 elsewhere; and wherein two identical submatrices are used to expand 1s in every column of H′_(b2), and paired submatrices are used to expand an even number of 1s in h_(b).
 17. The method of claim 16 wherein H_(b) is expanded by replacing each entry of H_(b) with a size z×z submatrix to produce H.
 18. The method of claim 16 wherein H_(b) is expanded by replacing each zero element of H_(b) with a zero submatrix of size z×z to produce H.
 19. The method of claim 16 wherein H_(b) is expanded by replacing each non-zero element of H_(b) with a non-zero submatrix to produce H.
 20. The method of claim 16 wherein H_(b) is expanded by replacing each non-zero element of H_(b) with a non-zero permutation submatrix to produce H.
 21. The method of claim 16 wherein: $\begin{matrix} {H_{b2} = \left\lbrack {h_{b}❘H_{b2}^{\prime}} \right\rbrack} \\ {{= \begin{bmatrix} {h_{b}(0)} & 1 & \; & \; & \; & \; \\ {h_{b}(1)} & 1 & 1 & \; & 0 & \; \\ \vdots & \; & 1 & ⋰ & \; & \; \\ \vdots & \; & \; & ⋰ & 1 & \; \\ \vdots & \; & 0 & \; & 1 & 1 \\ {h_{b}\left( {m_{b} - 1} \right)} & \; & \; & \; & \; & 1 \end{bmatrix}},} \end{matrix}$ where vector h_(b) has an odd weight w_(h)>=3.
 22. An apparatus comprising: storage means for storing a matrix H; a microprocessor using a matrix H to determine parity-check bits; and a transmitter for transmitting the parity-check bits; wherein H is an expansion of a base matrix H_(b) with H_(b) comprising a section H_(b1) and a section H_(b2), with H_(b2) comprising a first part comprising a column h_(b) having an odd weight greater than 2, and a second part H′_(b2) comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, 0 elsewhere; and wherein two identical submatrices are used to expand 1s in every column of H′_(b2), and paired submatrices are used to expand an even number of 1s in h_(b).
 23. The apparatus of claim 22 wherein: $\begin{matrix} {H_{b2} = \left\lbrack {h_{b}❘H_{b2}^{\prime}} \right\rbrack} \\ {{= \begin{bmatrix} {h_{b}(0)} & 1 & \; & \; & \; & \; \\ {h_{b}(1)} & 1 & 1 & \; & 0 & \; \\ \vdots & \; & 1 & ⋰ & \; & \; \\ \vdots & \; & \; & ⋰ & 1 & \; \\ \vdots & \; & 0 & \; & 1 & 1 \\ {h_{b}\left( {m_{b} - 1} \right)} & \; & \; & \; & \; & 1 \end{bmatrix}},} \end{matrix}$ where vector h_(b) has an odd weight w_(h)>=3.
 24. An apparatus comprising: storage means for storing a matrix H; a receiver for receiving a signal vector y=(y₀ . . . y_(n−1)); and a microprocessor using a matrix H to determine a current symbol set (s₀, . . . , s_(k−1)), wherein H is an expansion of a base matrix H_(b) and wherein H_(b) comprises a section H_(b1) and a section H_(b2), and wherein H_(b2) comprises a first part comprising a column h_(b) having an odd weight greater than 2, and a second part H′_(b2) comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, 0 elsewhere; and wherein two identical submatrices are used to expand is in every column of H′_(b2), and paired submatrices are used to expand an even number of 1s in h_(b).
 25. The apparatus of claim 24 wherein: $\begin{matrix} {H_{b2} = \left\lbrack {h_{b}❘H_{b2}^{\prime}} \right\rbrack} \\ {{= \begin{bmatrix} {h_{b}(0)} & 1 & \; & \; & \; & \; \\ {h_{b}(1)} & 1 & 1 & \; & 0 & \; \\ \vdots & \; & 1 & ⋰ & \; & \; \\ \vdots & \; & \; & ⋰ & 1 & \; \\ \vdots & \; & 0 & \; & 1 & 1 \\ {h_{b}\left( {m_{b} - 1} \right)} & \; & \; & \; & \; & 1 \end{bmatrix}},} \end{matrix}$ where vector h_(b) has an odd weight w_(h)>=3. 